1. Field of the Invention
The present invention relates to an apparatus for accessing a dynamic random access memory (DRAM), and more particularly to an apparatus for converting a conventional fast page mode DRAM to conform to the specification of an extended data output (EDO) DRAM.
2. Description of the Prior Art
Dynamic random access memory (DRAM) is one of important elements used in almost every digital electronic system, such as a personal computer or a video graphics array (VGA) adapter. More than ninety percent of those DRAM chips which are employed in electronic devices and are available in stock belong to fast page mode (FPM) type DRAM as shown in FIG. 1. When the row address strobe (RAS/) signal from a central processing unit (CPU) goes low, the DRAM 10 accepts the supplied address from system address bus 12 and uses it as a row address. If the column address strobe (CAS/) signal is low, the DRAM 10 accepts the supplied address from system address bus 12 and uses it as a column address. When the read/write (WE/) signal, which is also called write enable signal, goes low, the DRAM 10 carries out a write operation; otherwise data is read from a system data bus 14. While the signal at the output enable (OE/) pin is low, the data from the DRAM 10 are coupled to the system data bus 14.
FIG. 2 shows a typical timing diagram of the FPM DRAM. At the transition when the signal CAS/ goes from low to high, the valid data N on the system data bus are deactivated as designated in number 20. Before CAS/ goes low again to activate another valid data N+1, a precharge time 22 is required during which there is no valid data on the bus. Therefore, the CAS/ has to stay low wastefully before the data are no longer needed.
Even though the speed of the FPM DRAM is improved somewhat by the improvement in semiconductor technology, it is still unable to catch up with the other elements, such as a CPU, of the system. Consequently some evolutionary DRAMs such as EDRAM, SDRAM and CDRAM or some revolutionary ones such as Rambus DRAM are designed to overcome drawback of a conventional FPM DRAM. However, those new type DRAMs, which work in quite different ways when compared with the FPM DRAM, accommodate difficultly to most today's system architectures.
Extended data output (EDO) DRAM is one exception that utilizes the same control signals and the same coupling as described in FIG. 1. Owing to some modification in the timing, the EDO DRAM largely improves its performance for more than forty percentage. FIG. 2B shows a timing diagram of an EDO DRAM. At the transition when the signal CAS/ goes from low to high designated as 24, the valid data N will not be turned down until the CAS/ goes low again. As a consequence, a precharge 26 can be performed before the valid data N are deactivated. Noticeably, the valid data will be turned down when signal OE/ is high, or signal WE/ is low, or both signals RAS/ and CAS/ go high.
While some chip sets that can manipulate EDO DRAM are employed in some electronic systems, the EDO DRAM is at a disadvantage when compared with the FPM DRAM regarding to the price and availability. Therefore, a need has arisen for an adapter that can convert a FPM DRAM to conform to the specification of an EDO DRAM.